IS43QR16256B-083RBLI

IS43QR16256B-083RBLI 256Mx16 DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with eight banks (2 bank groups each with 4 banks). The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operations to the DDR4 SDRAM are burst-oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence.

• Standard voltage is VDD = VDDQ = 1.2V, VPP=2.5V
• Data integrity, auto self refresh (ASR) by DRAM built-in TS, auto refresh and self refresh modes
• DRAM access bandwidth, separated IO gating structures by bank groups, self refresh abort
• Signal synchronization, write levelling via MR settings, read levelling via MPR
• Reliability and error handling, command/address parity, data bus write CRC, MPR readout
• Signal integrity, internal VREFDQ training, read preamble training, gear down mode
• Power saving and efficiency, POD with VDDQ termination, command/address latency (CAL)
• 96-ball FBGA package
• Industrial temperature rating range from -40°C to +95°C
• Speed grade (CL-TRCD-TRP) is 2400Mbps/16-16-16