IS43LD32640B-18BLI

IS43LD32640B-18BLI is a 64Mb x 32 mobile CMOS LPDDR2 S4 SDRAM. The device is organized as 8 banks of 16Meg words of 16bits or 8Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4n bits are prefetched to achieve very high bandwidth.

• VDD2=1.14 to 1.3V, VDDCA/VDDQ=1.14 to 1.3V, VDD1=1.7 to 1.95V low-voltage core/I/O power supplies
• High speed un-terminated logic(HSUL_12) I/O interface
• 533MHz clock frequency
• Four-bit pre-fetch DDR architecture, multiplexed, double data rate, command/address inputs
• Bidirectional/differential data strobe per byte of data (DQS/DQS#)
• Programmable read/write latencies(RL/WL) and burst lengths(4, 8 or 16), ZQ calibration
• On-chip temperature sensor to control self refresh rate
• Partial –array self refresh(PASR), deep power-down mode(DPD)
• Industrial temperature range from -40°C to +85°C
• 134 ball BGA package