AS1C8M16PL-70BIN

AS1C8M16PL-70BIN is a 128M (4Mx16bit CellularRAM AD-MUX *2 stack) low-power PSEUDO SRAM. It is a high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb CellularRAM device has a DRAM core organized as 4 Meg x 16bits. This device is a variation of the industry-standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality dramatically reduce the required signal count and increase read/write bandwidth. It includes two mechanisms to minimize standby currents. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature-compensated self refresh (TCSR) uses an on-chip sensor to adjust the refresh rate to match the device temperature refresh rate decreases at lower temperatures to minimize current consumption during standby. The system configurable refresh mechanisms are accessed through the RCR.

• 16-bit multiplexed address/data bus, single device supports asynchronous and burst operation
• 1.7V to 1.95V VCC/VCCQ voltage, 100µA² power dissipation (standby (ISB1, typ.,25°C))
• Random access time is 70ns, tACLK is 7ns at 108MHz, 5.5ns at 133MHz
• Burst mode READ and WRITE access: 4, 8, 16 or 32 words or continuous burst, burst wrap or sequential
• Low power consumption: asynchronous READ: <lt/>25mA, continuous burst READ: <lt/>35mA
• Initial access, burst READ: (37.0ns [4 clocks] at 108 MHz) <lt/>35mA
• Continuous burst READ: <lt/>30mA initial access, burst READ: (37.5ns [5 clocks] at 133MHz) <lt/>40mA
• On-chip temperature compensated self-refresh (TCSR)
• Partial array refresh (PAR), deep power-down(DPD) mode
• Operating temperature range from -30 to 85°C, x16 interface bus, 49-ball FBGA package