MPC8247CVRTIEA

The MPC82xx series PowerQUICC II Processor with PCI, USB and communications processor module. It include on a single-chip a 32-bit Power Architecture® core that incorporates memory management units (MMUs) and instruction and data caches and that implements the power architecture instruction set, a modified communications processor module (CPM) and an integrated security engine (SEC) for encryption (the MPC8272 and the MPC8248 only). It targets networking equipment requiring encryption capabilities, such as small and medium enterprise (SME) routers, VPN and firewall routers, wireless access points, residential gateways and xDSL equipment. It features dual-core architecture that combines the 603e core with a separate RISC-based communications processor module. High-performance operation with CPU frequencies scaling to 400MHz, CPM frequencies at up to 200MHz and bus speeds up to 100MHz.

• Separate 16kB data and instruction caches
• Power Architecture®-compliant memory management unit (MMU)
• Common on-chip processor (COP) test interface
• Supports bus snooping for cache coherency
• Low-power consumption
• 64-bit data and 32-bit address 60x bus
• 60x-to-PCI bridge
• System interface unit (SIU) - Clock synthesizer, reset controller and real-time clock (RTC) register
• Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, flash and other user-definable peripherals
• Disable CPU mode
• Communications processor module (CPM)
• Universal serial bus (USB) controller
• Serial DMA channel for receive and transmit on all serial channels
• Parallel I/O registers with open-drain and interrupt capability
• Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
• Two serial management controllers (SMCs), identical to those of the MPC860
• One serial peripheral interface identical to the MPC860 SPI
• One I²C controller (identical to the MPC860 I²C controller)
• Four independent 16-bit timers that can be interconnected as two 32-bit timers
• Smooth migration path for PowerQUICC™ and PowerQUICC II processor-based designs