MT47H64M8SH-25E:H

MT47H64M8SH-25E:H is a DDR2 SDRAM. It uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single READ or WRITE operation for the DDR2 SDRAM effectively consists of a single 4n-bitwide, two-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.

• 64M8 configuration, tCK = 2.5ns, CL = 5 cycle time
• VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible), differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture, duplicate output strobe (RDQS) option for x8
• DLL to align DQ and DQS transitions with CK, 4 internal banks for concurrent operation
• Programmable CAS latency (CL), posted CAS additive latency (AL)
• Adjustable data-output drive strength, on-die termination (ODT)
• Package style is 60-ball FBGA