MT40A2G8SA-062E:F

MT40A2G8SA-062E:F is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x8 configurations. This memory uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• 2Gig x 8 configuration, data rate is 3200MT/s, 1.2V pseudo open-drain I/O
• Packaging style is 78-ball FBGA
• Timing (cycle time) is 0.65ns at CL = 22 (DDR4-3200)
• Operating temperature range is 0°C to 95°C
• Operating supply voltage range is 1.14Vmin
• 8n-bit prefetch architecture, programmable data strobe preambles
• Multipurpose register READ and WRITE capability, self refresh mode
• Low-power auto self refresh (LPASR), temperature controlled refresh (TCR)
• Maximum power saving, output driver calibration, fine granularity refresh
• Databus write cyclic redundancy check (CRC), per-DRAM addressable