S80KS2562GABHI020

S80KS2562GABHI020 is a 256Mb, high-speed CMOS, HYPERRAM™ self-refresh dynamic RAM (DRAM) with HYPERBUS™ interface. DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by HYPERBUS™ interface host. Since host is not required to manage any refresh operations, the DRAM array appears to the host as though memory uses static cells that retain data without refresh. Hence, memory is more accurately described as pseudo static RAM (PSRAM). Since DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The host must confine the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh operation is needed.

• 1.8V interface support, single-ended clock (CK) - 11 bus signals
• Chip select (CS#), 8-bit data bus (DQ[7:0]), hardware reset (RESET#)
• Bidirectional read-write data strobe (RWDS), input during write transactions as write data mask
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read data strobe
• 200MHz maximum clock rate, DDR - transfers data on both edges of the clock
• Data throughput up to 400MBps (3,200Mbps), configurable burst characteristics
• Maximum access time (tACC) is 35ns, 1.55mA standby current (105 °C)
• 24-ball FBGA package
• Industrial temperature range from -40°C to + 85°C