S80KS2562GABHB020

S80KS2562GABHB020 is a HYPERRAM™ self-refresh dynamic RAM (DRAM) with HYPERBUS™ interface. It is a high-speed CMOS, self-refresh DRAM with HYPERBUS™ interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ interface host. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as pseudo-static RAM (PSRAM). Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfer lengths to allow internal logic refresh operations when they are needed.

• 1.8V interface support, single-ended clock (CK) - 11 bus signals
• Bidirectional read-write data strobe (RWDS), input during write transactions as write data mask
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read data strobe
• 200MHz maximum clock rate, DDR - transfers data on both edges of the clock
• 256Mb density
• VCC power supply range from 1.7 to 2V
• VCC standby current is 470µA typ at CS# = VCC, VCC = VCC max; full array
• 24-ball FBGA package
• Automotive, AEC-Q100 grade2 (-40°C to +105°C) temperature range