CY7C1380KV33-167AXI

CY7C1380KV33-167AXI is a pipelined SRAM that integrates with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (active low CE1), depth-expansion chip enables (active low CE2 and CE3), burst control inputs (ADSC, ADSP, and active low ADV), write enables (active low BWX, and active low BWE), and global write (active low GW). Asynchronous inputs include the output enable (active low OE) and the ZZ pin. Address and chip enable is registered at rising edge of clock when address strobe processor (active low ADSP) or address strobe controller (active low ADSC) is active. Subsequent burst address can be internally generated as this is controlled by the advance pin (active low ADV).

• 65nm process technology, 3.3V VDD, 167MHz speed
• Registered inputs and outputs for pipelined operation
• 3.4ns maximum access time, 163mA maximum operating current
• Provides high performance 3-1-1-1 access rate
• Separate processor and controller address strobes
• Synchronous self-timed write, asynchronous output enable, single cycle chip deselect
• IEEE 1149.1 JTAG-compatible boundary scan
• Power supply voltage range from 3.135 to 3.6V
• Input/output capacitance is 5pF (TA=25°C, f=1MHz, VDD=3.3V, VDDQ=2.5V)
• 100-pin TQFP package, industrial temperature range from -40 to +85°C