5M160ZE64C5N

5M160ZE64C5N is a MAX® V family of low cost and low power CPLD. It offers more density and I/Os per footprint versus other CPLDs. The MAX V device family features standby current as low as 25µA and fast power-down/reset operation, fast propagation delay and clock-to-output times, internal oscillator, Emulated RSDS output support with a data rate of up to 200Mbps, Emulated LVDS output support with a data rate of up to 304Mbps, four global clocks with two clocks available per logic array block (LAB), User flash memory block up to 8Kbits for non-volatile storage with up to 1000 read/write cycles, bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors, I/Os are fully compliant with the PCI-SIG® PCI Local Bus Specification, revision 2.2 for 3.3V operation, Schmitt triggers enabling noise tolerant inputs (programmable per pin), hot-socket compliant.

• Low-cost, low-power, and non-volatile CPLD architecture
• 160 logic elements, Instant-on (0.5ms or less) configuration time, 5 speed grade
• Single 1.8V external supply for device core
• MultiVolt I/O interface supporting 3.3V, 2.5V, 1.8V, 1.5V and 1.2V logic levels
• 128 typical equivalent macrocells
• 8,192bits user flash memory size, 4 global clocks, 1 internal oscillator
• 79 max user I/Os, 7.5ns tPD1, 152MHz fCNT, 2.3ns tSU, 6.5ns tCO
• Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990
• 64 pin plastic enhanced quad flat pack (EQFP)
• Commercial temperature range from (TJ) 0°C to 85°C