LPC3240FET296/01,5

The LPC3240FET296/01,5 is a 16/32-bit Microcontroller based on ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go. The device operates at CPU frequencies of up to 266MHz. The implementation uses an ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline and an integral memory management unit (MMU). The MMU provides the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The ARM926EJ-S also has a hardware based set of DSP instruction extensions, which includes single cycle MAC operations and hardware based native Jazelle Java byte-code execution. The implementation has a 32kB instruction cache and a 32kB data cache. For low power consumption the device takes advantage of advanced technology development to optimize intrinsic power and uses software controlled architectural enhancements to optimize application based power management.

• Vector floating point (VFP) coprocessor
• Selectable boot-up from various external devices: NAND flash, SPI memory, USB, UART or static memory
• Multi-layer AHB system
• External memory controller for DDR and SDR SDRAM as well as for static devices
• 2 NAND flash controllers - single-level NAND flash devices and multi-level NAND flash devices
• Eight channel general purpose DMA (GPDMA) controller
• 10/100 Ethernet MAC with dedicated DMA controller
• USB interface supporting either device, host (OHCI compliant) or OTG
• LCD controller - Supporting both STN and TFT panels
• Secure digital (SD) memory card interface
• 400kHz 10-bit ADC
• Real-time clock (RTC) with separate power pin
• 32-bit general purpose high-speed timer with a 16-bit pre-scaler
• Watchdog timer clocked by the peripheral clock
• Two single-output PWM blocks
• Motor control PWM
• Keyboard scanner function allows automatic scanning of an up to 8 x 8 key matrix
• Up to 18 external interrupts
• Standard ARM test/debug interface for compatibility with existing tools
• Emulation trace buffer (ETB) with 2048 x 24 bit RAM allows trace via JTAG
• Stop mode saves power while allowing many peripheral functions to restart CPU activity
• On-chip crystal oscillator
• Boundary scan for simplified board testing
• User-accessible unique serial ID number for each chip