MT47H32M16NF-25E:H

MT47H32M16NF-25E:H is a DDR2 SDRAM. The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. The DDR2 SDRAM provides programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time.

• VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
• JEDEC-standard 1.8V I/O (SSTL-18-compatible)
• DLL to align DQ and DQS transitions with CK, 4 internal banks for concurrent operation
• Programmable CAS latency (CL), posted CAS additive latency (AL)
• Adjustable data-output drive strength, 64ms, 8192-cycle refresh
• On-die termination (ODT), supports JEDEC clock jitter specification
• 32 Meg x 16 configuration
• Timing – cycle time : 2.5ns at CL = 5 (DDR2-800)
• 84-ball FBGA package
• Commercial operating temperature range from (0°C ≤ TC ≤ +85°C)