MT46H16M32LFB5-5 IT:C

MT46H16M32LFB5-5 IT:C is a mobile LPDDR SDRAM. The 512Mb mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 134,217,728-bit banks are organized as 8192 rows by 1024 columns by 16 bits. Each of the x32’s 134,217,728-bit banks are organized as 8192 rows by 512 columns by 32 bits.

• 1.8/1.8V operating voltage, differential clock inputs (CK and CK#)
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
• Commands entered on each positive CK edge, clock stop capability
• DQS edge-aligned with data for READs; center aligned with data for WRITEs
• 4 internal banks for concurrent operation, data masks (DM) for masking write data; one mask per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16, concurrent auto precharge option is supported
• Auto refresh and self refresh modes, 1.8V LVCMOS-compatible inputs
• 200MHz clock rate, 5.0ns access time, 16 Meg x 32 configuration, JEDEC-standard addressing
• 90-ball VFBGA package, -40°C to +85°C industrial operating temperature range