AS4C1G16D4-062BCN

AS4C1G16D4-062BCN DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• On-die, internal, adjustable VREFDQ generation, VDD = VDDQ = 1.2V ±60mV
• 1.2V pseudo open-drain I/O, 8 internal banks (x16): 2 groups of 4 banks each
• 8n-bit prefetch architecture, programmable data strobe preambles
• Data strobe preamble training, command/address latency (CAL), command/address (CA) parity
• Multipurpose register READ and WRITE capability, write levelling, self refresh mode
• Low-power auto self-refresh (LPASR), temperature-controlled refresh (TCR)
• Fine granularity refresh, self refresh abort, maximum power saving, output driver calibration
• Nominal, park, and dynamic on-die termination (ODT), data bus inversion (DBI) for data bus
• Databus write cyclic redundancy check (CRC), Per-DRAM addressability, JEDEC JESD-79-4 compliant
• 96-ball FBGA package, commercial temperature range from 0°C to 95°C