MT53E1536M32D4DT-046 WT:A

MT53E1536M32D4DT-046 WT:A is a mobile LPDDR4 SDRAM. The low-power DDR4 SDRAM (LPDDR4) is a high-speed CMOS, dynamic random-access memory. The device is internally configured with x16 I/O, 8-banks. LPDDR4 uses a double-data-rate (DDR) protocol on the DQ bus to achieve high-speed operation. The DDR interface transfers two data bits to each DQ lane in one clock cycle and is matched to a 16n-prefetch DRAM architecture. A write/read access consists of a single 16n-bit-wide data transfer to/from the DRAM core and 16 corresponding n-bit-wide data transfers at the I/O pins.

• 16n prefetch DDR architecture, 8 internal banks per channel for concurrent operation
• Single-data-rate CMD/ADR entry, bidirectional/differential data strobe per byte lane
• Programmable READ and WRITE latencies (RL/WL), programmable and on-the-fly burst lengths (BL=16, 32)
• Directed per-bank refresh for concurrent bank operation and ease of command scheduling
• On-chip temperature sensor to control self refresh rate
• Partial-array self refresh (PASR), selectable output drive strength (DS), clock-stop capability
• 6GB (48Gb) total density, 4266Mb/s data rate per pin
• 1.10V VDD2/0.60V or 1.10V VDDQ operating voltage
• 200-ball VFBGA package
• Operating temperature from -30°C to +85°C