MT48LC16M16A2B4-6A:G

MT48LC16M16A2B4-6A:G is a 256Mb SDR SDRAM. It is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

• 16 Meg x 16 (4 Meg x 16 x 4 banks) configuration
• tWR = 2CLK write recovery (tWR)
• 6ns at CL = 3 (x8, x16 only) cycle time
• Fully synchronous; all signals registered on positive edge of system clock
• Internal, pipelined operation; column address can be changed every clock cycle
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• LVTTL-compatible inputs and outputs, single 3.3V ±0.3V power supply
• Fully synchronous; all signals registered on positive edge of system clock
• Automotive operating temperature range from -40°C to +105°C, package style is 54-ball VFBGA