MT44K32M36RB-107E:A

MT44K32M36RB-107E:A is a RLDRAM®3 high-speed memory device designed for high-bandwidth data storage-telecommunications, networking, cache applications, and so forth. The chip’s 16-bank architecture is optimized for sustainable high-speed operation. The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output data is referenced to the READ strobes. Commands, addresses, and control signals are also registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data strobes. The device is supplied with 1.35V for the core and 1.2V for the output drivers. The 2.5V supply is used for an internal supply. Bank-scheduled refresh is supported with the row address generated internally.

• 1.07ns tRC (MIN) = 8ns (RL3-1866) clock cycle, tRC timing, 32 Megx36 configuration, mirror function
• 1200MHz DDR operation (2400Mb/s/ball data rate), 86.4Gb/s peak bandwidth (x36 at 1200MHz clk freq)
• Organization 64 Meg x 18, and 32 Meg x 36 common I/O, 16 banks, output driver and ODT calibration
• 1.2V center-terminated push/pull I/O, reduced cycle time, SDR addressing, READ training register
• Programmable RL/WL latency and burst length, data mask for WRITE commands
• Differential input clocks, free-running differential input data clocks and output data clocks
• On-die DLL generates CK edge-aligned data and differential output data clock signals
• 64ms refresh (128K refresh per 64ms), integrated on-die termination, single or multibank writes
• READ training register, multiplexed and non-multiplexed addressing capabilities
• 168-ball BGA package, commercial operating temperature range from 0° to +95°C