MT40A512M16TB-062E IT:R

MT40A512M16TB-062E IT:R is a MT40A512M1 high-speed dynamic random-access memory that internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. This DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• 512M16 configuration, cycle time (CAS latency) is tCK= 0.625ns, CL = 22
• Connectivity test, sPPR and hPPR capability
• Programmable data strobe preambles, data strobe preamble training, command/address latency
• Write leveling, self refresh mode, low-power auto self refresh
• Temperature controlled refresh (TCR), fine granularity refresh, self refresh
• Maximum power saving, output driver calibration, nominal, park, and dynamic on-die termination
• Data bus inversion (DBI) for data bus, command/Address (CA)
• Databus write cyclic redundancy check (CRC), per-DRAM addressability
• Operating temperature is -40°C to 95°C (industrial)
• Package style is 96-ball FBGA