IS43TR16512BL-125KBL

IS43TR16512BL-125KBL is a DDR3 SDRAM. The DRAM samples CK - CK# status with the rising edge of DQS - DQS# and provides feedback on the DQ bus asynchronously after tWLO timing. In this product, all data bits ("prime DQ bit(s)"), which are DQ0~DQ7 for x8, or DQ0~DQ15 for x16, provide the leveling feedback.

• Standard voltage is VDD and VDDQ=1.5V ±0.075V
• High-speed data transfer rates with system frequency up to 933MHz
• 8 internal banks for concurrent operation, 8n-Bit pre-fetch architecture
• Programmable CAS latency, programmable additive latency: 0, CL-1, CL-2
• Programmable CAS WRITE latency (CWL) based on tCK
• BL switch on the fly, Auto Self Refresh(ASR), Self Refresh Temperature(SRT)
• OCD (Off-Chip Driver Impedance Adjustment), Dynamic ODT (On-Die Termination)
• 512Mx16 configuration, 1600MT/s data rate
• 96-ball BGA package
• Commercial operating temperature range from 0°C to +95°C