S26KL512SDABHI020

S26KL512SDABHI020 is a S26KL512S HYPERFLASH™ high-speed CMOS, MIRRORBIT™ NOR flash device with the HYPERBUS™ low signal count DDR interface, that achieves high speed read throughput. The DDR protocol transfers two data bytes per clock cycle on the data (DQ) signals. A read or write access for the HYPERFLASH™ consists of a series of 16-bit wide, one clock cycle data transfers at the internal HYPERFLASH™ core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. Command/address/write-data values are center aligned with the clock edges and read-data values are edge aligned with the transitions of RWDS. During linear operation accesses start at a selected location and continue in a sequential manner until the read operation is terminated, when CS# returns HIGH. Write transactions transfer one or more 16-bit values.

• 3.0V I/O, 11 bus signals, single ended clock, 8-bit data bus (DQ[7:0])
• 12 bus signals, differential clock (CK, CK#), chip select (CS#), advanced sector protection
• Read-write data strobe (RWDS), HYPERFLASH™ memories use RWDS only as a read data strobe
• Up to 333MBps sustained read throughput, DDR – two data transfers per clock
• 96ns initial random read access time, initial random access read latency: 5 to 16 clock cycles
• Wrapped or linear burst type selected in each transaction, configurable output drive strength
• INT# output to generate external interrupt, busy to ready transition, ECC detection
• RSTO# output to generate system level power-on reset, user configurable RSTO# LOW period
• 512Mb density, 100MHz speed, FBGA package
• Industrial temperature range from (–40°C to +85°C)