AS7C34096A-12JCN

AS7C34096A-12JCN is a high-performance CMOS 4,194,304-bit static random access memory (SRAM) device organized as 524,288 words × 8bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When active-low CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage.

• Organization: 524,288 words × 8bits, center power and ground pins
• High speed, equal access and cycle times
• Low power consumption, 650mW/max at 10ns active, 28.8mW/max CMOS standby
• Easy memory expansion with active-low CE, active-low OE inputs
• TTL-compatible, three-state I/O
• ESD protection ≥ 2000volts
• Latch-up current ≥ 200mA
• Access time is 12ns
• SOJ 400 mil package
• Commercial temperature range from 0°C to 70°C