AS4C512M8D4A-75BIN

AS4C512M8D4A-75BIN is a 512M x 8bit DDR4 synchronous DRAM (SDRAM). The DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with sixteen banks (4 bank groups each with 4 banks). The DDR4 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operations to the DDR4 SDRAM are burst-oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Activate Command, which is then followed by a Read or Write command.

• JEDEC standard compliant, supports JEDEC clock jitter specification
• Bidirectional differential data strobe, DQS and DQS#, differential clock, CK and CK#
• 16 internal banks: 4 groups of 4 banks each, separated IO gating structures by bank group
• 8n-bit prefetch architecture, precharge and active power down, auto refresh and self refresh
• Low-power auto self refresh (LPASR), self refresh abort, fine granularity refresh
• Dynamic ODT (RTT-PARK and RTT-Nom and RTT-WR), write levelling, DQ training via MPR
• Programmable preamble is supported both of 1tCK and 2tCK mode, command/address (CA) parity
• Read preamble training, control gear down mode, per DRAM addressability (PDA)
• ZQ calibration, command/address latency (CAL), maximum power saving mode (MPSM)
• 78-ball FBGA package, industrial temperature range from -40°C to 95°C