AS4C128M16D2A-25BCN

AS4C128M16D2A-25BCN 2Gb DDR2 is a high-speed CMOS double-data rate-two (DDR2), synchronous dynamic random-access memory (SDRAM) containing 2048 Mbits in a 16-bit wide data I/Os. It is internally configured as an 8-bank DRAM, 8 banks x 16Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, write latency= read latency -1, off-chip driver (OCD) impedance adjustment, and on-die termination(ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style. Accesses begin with the registration of a bank activate command, and then it is followed by a read or write command. A sequential and gapless data rate is possible depending on the burst length, CAS latency, and speed grade of the device.

• JEDEC standard compliant, JEDEC standard 1.8V I/O (SSTL-18-compatible)
• Power supplies: VDD and VDDQ=+1.8V ± 0.1V
• Supports JEDEC clock jitter specification, fully synchronous operation
• Differential clock, CK and CK#, bidirectional single/differential data strobe - DQS & DQS#
• Fast clock rate: 400MHz, 8 internal banks for concurrent operation, auto refresh and self refresh
• 4-bit prefetch architecture, internal pipeline architecture, precharge and active power down
• Programmable mode and extended mode registers, posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5
• Burst type: sequential / interleave, DLL enable/disable, on-die termination (ODT)
• Off-chip driver (OCD), impedance adjustment, adjustable data-output drive strength
• 128Mx 16 Org, commercial temperature range from 0°C to 85°C, 84-ball FBGA package