MT41K512M8DA-107 IT:P

MT41K512M8DA-107 IT:P is a DDR3L SDRAM. This DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

• Differential clock inputs (CK, CK#), 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL), programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Self-refresh temperature (SRT), automatic self refresh (ASR)
• Write leveling, multipurpose register, output driver calibration
• 512 Meg x 8 configuration
• 1866MT/s data rate, 13.91ns CL
• 78-ball FBGA package
• Industrial temperature range from -40°C ≤ TC ≤+95°C