LFE3-35EA-8FN484C

LFE3-35EA-8FN484C is an ECP3 (LatticeECP3 FPGA + SERDES) FPGA. It is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications. It is optimized with high performance and low cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, PLLs, DLLs, pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities. The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including DDR3, XGMII, and 7:1 LVDS.

• 1.2V voltage, slowest speed, LOW power, 33k logic controller
• Higher logic density for increased system integration
• Data rates 230Mbps to 3.2Gbps per channel for all other protocols
• Fully cascadable slice architecture, 12 to 160 slices for high performance multiply and accumulate
• Powerful 54-bit ALU operations, time division multiplexing MAC sharing
• Half 36x36, two 18x18, or four 9x9 multipliers
• Advanced 18x36 MAC and 18x18 Multiply-Multiply-Accumulate (MMAC) operations
• wo DLLs and up to ten PLLs per device
• DDR registers in I/O cells, dedicated read/write levelling functionality
• 484 lead fpBGA package, commercial operation junction temperature range from 0 to 85°C