S25FS256SAGBHI200

S25FS256SAGBHI200 is a S25FS256S series non-volatile serial peripheral interface (SPI) flash memory IC using MIRRORBIT™ technology - that stores two data bits in each memory array transistor, eclipse architecture - that dramatically improves program and erase performance and 65-nm process lithography. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 128 words (256bytes) or 256 words (512bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. It offers high densities coupled with the flexibility and fast performance required by a variety of embedded applications. This is ideal for code shadowing, XIP, and data storage.

• CMOS 3.0V core with versatile I/O, SPI clock polarity and phase modes 0 and 3
• Serial command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
• Multi I/O command set and footprint compatible with S25FL-P SPI family
• Common flash interface (CFI) data for configuration information, programming (1.5MBps)
• Automatic ECC-internal hardware error correction code generation with single bit error correction
• 100000 program-erase cycles minimum, 20 year data retention minimum
• OTP array of 1024bytes, block protection, advanced sector protection (ASP)
• Individual sector protection controlled by boot code/password, core supply voltage is 2.7 to 3.6V
• 256Mb density, 133MHz speed, 24-ball BGA package, industrial -40 to 85°C temperature
• EHPLC, 5 × 5 ball BGA footprint, uniform 64KB sectors with Hybrid 4KB sectors