MT53E256M32D2DS-053 AIT:B

MT53E256M32D2 is a mobile low-power DDR4 SDRAM (LPDDR4). It is a high-speed CMOS, dynamic random-access memory internally configured with either 1 or 2 channels. Each channel is comprised of 16 DQs and 8 banks. It uses a 2-tick, single-data-rate (SDR) protocol on the CA bus to reduce the number of input signals in the system. The term "2-tick" means that the command/ address is decoded across two transactions, such that half of the command/address is captured with each of two consecutive rising edges of CK. The 6-bit CA bus contains command, address, and bank information. Some commands such as READ, WRITE, MASKED WRITE, and ACTIVATE require two consecutive 2-tick SDR commands to complete the instruction. It uses a double-data-rate (DDR) protocol on the DQ bus to achieve high-speed operation. The DDR interface transfers two data bits to each DQ lane in one clock cycle and is matched to a 16n-prefetch DRAM architecture.

• Operating voltage is 1.10V VDD2/0.60V or 1.10V VDDQ
• 256 meg x 32 configuration
• 2 die count, on-chip temperature sensor to control self refresh rate
• Cycle time is 535ps, tCK RL = 32/36
• Clock rate is 1866MHz, data rate is 3733Mb/s/pin
• Single-data-rate CMD/ADR entry, bidirectional/differential data strobe per byte lane
• Directed per-bank refresh for concurrent bank operation and ease of command scheduling
• Partial-array self refresh (PASR), selectable output drive strength (DS), clock-stop capability
• Operating temperature range is -40°C to +95°C
• Package style is 200-ball TFBGA