MT40A2G8JC-062E:E

MT40A2G8JC-062E:E is a DDR4 SDRAM. It is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• 2 Gig x 8 configuration, tCK = 0.625ns, CL = 22 cycle time, CAS latency
• VDD = VDDQ = 1.2V ±60mV, VPP = 2.5V, –125mV, +250mV
• On-die, internal, adjustable VREFDQ generation, 1.2V pseudo open-drain I/O
• 16 internal banks (x4, x8): 4 groups of 4 banks each
• 8n-bit prefetch architecture, programmable data strobe preambles
• Data strobe preamble training, command/address latency (CAL)
• Multipurpose register READ and WRITE capability, write levelling
• Self refresh mode, low-power auto self refresh (LPASR), temperature controlled refresh (TCR)
• Fine granularity refresh, self refresh abort, maximum power saving
• 78-ball FBGA package, commercial temperature range from 0 to 95°C