USB3280-AEZG

The USB3280-AEZG is an USB 2.0 Physical Layer Transceiver (PHY) Integrated Circuit features low power dissipation, which is ideal for building a bus powered USB 2.0 peripheral. The PHY uses an 8-bit bidirectional parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol at 12Mbps. All required termination and 5.25V short circuit protection of the DP/DM lines are internal to the chip. The USB3280 also has an integrated 1.8V regulator so that only a 3.3V supply is required. While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.

• USB-IF Hi-Speed certified to USB 2.0 electrical specification
• Internal short circuit protection of DP and DM lines
• On-chip oscillator operates with low cost 24MHz crystal
• Latch-up performance exceeds 150mA per EIA/JESD 78, Class II
• SYNC and EOP generation on transmit packets and detection on receive packets
• NRZI encoding and decoding
• Bit stuffing and unstuffing with error detection
• Supports the USB suspend state, HS detection, HS chirp, reset and resume
• Support for all test modes defined in the USB 2.0 specification
• 55mA Typical un-configured current
• 83uA Typical suspend current