MPC5554AZP132

The MPC5554AZP132 is a 32-bit Microcontroller a member of the MPC5500 family of microcontrollers built on the power architecture embedded technology. This family of parts has many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC500 family. The host processor core of this device complies with the power architecture embedded category that is 100% user-mode compatible (including floating point library) with the original PowerPC instruction set. The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original PowerPC instruction set. The device has two levels of memory hierarchy. The fastest accesses are to the 32kB unified cache. The next level in the hierarchy contains the 64kB on-chip internal SRAM and 2MB internal flash memory.

• High-performance 132MHz 32-bit power Architecture technology e200z6 core
• Memory management unit (MMU)
• Signal processing extension - DSP, SIMD and floating point capabilities
• 2 Enhanced time processor units (eTPUs)
• 64-channel Enhanced direct memory access (eDMA) controller
• Interrupt controller (INTC) capable of handling 286 selectable-priority interrupt sources
• Frequency modulated phase-locked loop (FMPLL) to assist in EMI management
• MPC500 compatible external bus interface
• Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities
• 40-channel Dual eQADC
• 4 Deserial serial peripheral interface (DSPI)
• Interface (DSPI) modules - 16 bits wide, up to six chip selects each
• 3 Controller area network (CAN) modules with 64 buffers each
• 2 Enhanced serial communication interface modules (eSCI)