AD9542BCPZ

AD9542 is a quad input, five-output, dual DPLL synchronizer and adaptive clock translator. The 10 clock outputs of this are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. Typical applications are SyncE jitter cleanup and synchronization, optical transport networks (OTN), SDH, and macro and small cell base stations, OTN mapping/demapping with jitter cleaning, small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control, JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking, cable infrastructures, carrier Ethernet.

• Cross point mux interconnects reference inputs to PLLs
• Supports embedded (modulated) input/output clock signals
• External EEPROM support for autonomous initialization
• Fast DPLL locking modes
• External EEPROM support for autonomous initialization
• Typical power dissipation configuration is 560mW (typical values apply for VDD=1.8V)
• Typical full power-down is 125mW (typical values apply for VDD=1.8V)
• Typical input reference on/off (single-ended) is 13mW (fREF=19.44MHz)
• Output frequency range from 2250 to 2415MHz
• 48-lead LFCSP package, temperature range from -40°C to +85°C

Notes

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party