S25FS256SAGNFI001

S25FS256SAGNFI001 is a FS-S flash non-volatile memory using MIRRORBIT™ technology - that stores two data bits in each memory array transistor, eclipse architecture - that dramatically improves program and erase performance, 65-nm process lithography. The S25FS-S family connects to a host system via a serial peripheral interface (SPI). This multiple width interface is called SPI multi-I/O or MIO. In addition, this is double data rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The FS-S Eclipse architecture features a page programming buffer that allows up to 512bytes to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

• 256Mbit density, 65nm MIRRORBIT™ Process Technology, 133MHz SDR speed
• 8-contact WSON package, industrial temperature range from -40 to + 85°C
• SPI clock polarity and phase modes 0 and 3
• Normal, fast, dual I/O, quad I/O, DDR quad I/O, modes burst wrap, continuous (XIP), QPI
• Serial flash discoverable parameters and common flash interface for configuration information
• 256 or 512byte page programming buffer, program suspend and resume
• Automatic ECC internal hardware error correction code generation with single-bit error correction
• Erase suspend and resume, erase status evaluation, one-time program (OTP) array of 1024bytes
• 100000 program-erase cycles (minimum), 20 year data retention (minimum)
• 100000 program-erase cycles (minimum), 20 year data retention (minimum)