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TFP401APZP - 

DVI RECEIVER, 3.6V, TQFP-100

TEXAS INSTRUMENTS TFP401APZP

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Manufacturer Part No:
TFP401APZP
Newark Part No.:
74K3959

Product Information

:
0°C
:
-
:
Each
:
70°C
:
DVI
:
100Pins
:
TQFP
:
3V
:
-
:
3.6V
:
MSL 3 - 168 hours
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Product Overview

The TFP401APZP is a TI PanelBus™ DVI Receiver, HSYNC fix. The TI PanelBus™ flat-panel display product, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP401APZP finds applications in any design requiring high-speed digital interface. The TFP401APZP supports display resolutions up to 1080p and WUXGA in 24-bit true-colour pixel format. The TFP401APZP offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels and provides an option for time-staggered pixel outputs for reduced ground bounce. PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint and ultralow ground inductance. The TFP401APZP combines PanelBus circuit innovation with TI's advanced 0.18µm EPIC-5 CMOS process technology, along with TI PowerPAD package technology to achieve a reliable, low-powered, low-noise, high-speed digital interface solution.
  • Supports pixel rates up to 165MHz (including 1080p and WUXGA at 60Hz)
  • Digital visual interface (DVI) specification compliant
  • True-colour, 24-bit/pixel, 16.7M colours at 1 or 2 pixels per clock
  • Laser trimmed internal termination resistors for optimum fixed impedance matching
  • Skew tolerant up to one pixel-clock cycle
  • 4x Oversampling
  • Reduced power consumption - 1.8V core operation with 3.3V I/Os and supplies
  • Reduced ground bounce using time-staggered pixel outputs
  • Incorporates HSYNC jitter immunity
  • Green product and no Sb/Br

Applications

Consumer Electronics, Computers & Computer Peripherals, Imaging, Video & Vision, Multimedia

Warnings

Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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