Evaluation Module, Low Additive Jitter Clock Buffer, CDCLVD1204

CDCLVD1204EVM - Evaluation Module, Low Additive Jitter Clock Buffer, CDCLVD1204

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Product Overview

The CDCLVD1204EVM evaluation module is designed to demonstrate the electrical performance of the CDCLVD1204. The CDCLVD1204 are high performance, low additive jitter clock buffers. They have two universal input buffers that support single ended or differential clock inputs and are selectable through a control pin. The devices also feature On chip bias generators that can provide the LVDS common mode voltage to the device inputs. The CDCLVD1204 is specifically designed for driving 50Ohm transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage should be applied to the unused negative input pin. The evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVD1204 or CDCLVD2102. However, this EVM can also be used for customers interested in the CDCLVD1208 or CDCLVD2104 as well.
  • Easy to use evaluation board to fan out Low phase noise clocks
  • Easy device setup
  • Fast configuration
  • Control pins configurable through jumpers
  • Board powered at 2.5V
  • Single ended or differential input clocks
  • Device supports four LVDS outputs, EVM supports two LVDS outputs


Communications & Networking, Medical, Test & Measurement, Wireless, Clock & Timing


It is important to operate this EVM within the input voltage range of -0.2V to Vcc +0.2V and the output voltage range of -0.2V to Vcc +0.2V .


These devices have limited built in ESD protection. The leads should be shorted together or device placed in conductive foam during storage or handling to prevent electrostatic damage to MOS gates.

Product Information

Texas Instruments
Clock & Timing
Clock Buffer
SCAS898, 2:4 Low Additive Jitter LVDS Buffer (Rev. A), 4 LVDS Outputs Clock Buffer Evaluation Board
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