MC100EP32DG - 

ECL Divide-by-2 Divider, 4 GHz, 3.3 V / 5 V, SOIC-8

MC100EP32DG - ECL Divide-by-2 Divider, 4 GHz, 3.3 V / 5 V, SOIC-8

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Product Overview

The MC100EP32DG is an integrated ECL ÷2 Divider with differential CLK inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01μF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state, the reset allows for the synchronization of multiple EP32's in a system. The 100 series contains temperature compensation.
  • Open input default state
  • Safety clamp on inputs
  • Q Output will default low with inputs open or at VEE
  • 350ps Propagation delay



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