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Product Information

  • Architecture: ARM Cortex-M0
  • CPU Speed: 48MHz
  • Controller Family/Series: PSoC 4
  • Core Size: 32bit
  • Embedded Interface Type: I2C, SPI, UART
  • MCU Case Style: LQFP
  • MSL: MSL 3 - 168 hours
  • No. of I/O's: 36
  • No. of Pins: 44
  • Operating Temperature Max: 85°C
  • Operating Temperature Min: -40°C
  • Packaging: Each
  • Peripherals: ADC, DAC, DMA, LCD Controllers, PWM, Timer
  • Program Memory Size: 32KB
  • Program Memory Size: 32KB
  • RAM Memory Size: 4KB
  • SVHC: To Be Advised
  • Supply Voltage Max: 5.5V
  • Supply Voltage Min: 1.71V


The CY8C4245AXI-483 is a PSoC® 4 Microcontroller, scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analogue and digital blocks with flexible automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high-performance analogue-to-digital conversion, op-amps with comparator mode and standard communication and timing peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analogue and digital subsystems allow flexibility and in-field tuning of the design.


  • 48MHz ARM Cortex-M0 CPU with Single Cycle Multiply, up to 32kb Flash with Read Accelerator
  • Two Op-amps with reconfigurable high-drive external and high-bandwidth internal drive
  • 12-bit, 1Msps SAR ADC with Differential/Single-ended modes, channel sequencer with signal averaging
  • Two Current DACs (IDACs) for General-purpose or Capacitive Sensing Applications on Any Pin
  • Two Low-power Comparators that Operate in Deep Sleep Mode
  • Four Programmable Logic Blocks called Universal Digital Blocks, each with 8 Macrocells & Data path
  • Cypress-provided Peripheral Component Library, User-defined State Machines and Verilog Input
  • Low-power 1.71 to 5.5V operation, 20nA stop mode with GPIO pin wakeup, hibernate & deep sleep mode
  • Cypress CapSense Sigma-Delta (CSD) Provides Best-in-class SNR (5:1) and Water Tolerance
  • Cypress-supplied software component makes capacitive sensing design easy automatic hardware tuning
  • Segment LCD drive, LCD drive supported on all pins, operates in sleep mode with 4-bit per pin memory
  • Run-time reconfigurable Serial Communication Blocks with reconfigurable I²C, SPI, UART functionality
  • Four 16-bit Timer/Counter Pulse-width Modulator (TCPWM) Blocks
  • Centre-aligned, Edge and Pseudo-random Modes
  • Comparator-based triggering of kill signals for Motor Drive and other Digital Logic applications
  • 36 GPIO pins can be CapSense, LCD, Analogue or Digital, Drive modes & Slew rates are Programmable
  • Integrated Development Environment (IDE) provides schematic design entry and build
  • Applications Programming Interface (API) component for all fixed-function & programmable peripherals
  • After Schematic Entry, Development can be Done with ARM-based Industry-standard Development Tools


  • Motor Drive & Control
  • Computers & Computer Peripherals

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