AT91SAM9G45C-CU - 

ARM Microcontroller, SMART ARM926EJ-S, SMART ARM based Microcontrollers, 32bit, 400 MHz, 64 KB

AT91SAM9G45C-CU - ARM Microcontroller, SMART ARM926EJ-S, SMART ARM based Microcontrollers, 32bit, 400 MHz, 64 KB

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Newark Part No.:
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SMART ARM based Microcontrollers
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Product Overview

The AT91SAM9G45C-CU is a SMART 32-bit Embedded Microprocessor Unit based on ARM926EJ-S-based processor, features the frequently demanded combination of user interface functionality and high data rate connectivity, including LCD controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400MHz and multiple 100+ Mbps data rate peripherals, the SAM9G45 provides adequate performance and bandwidth to the network or local storage media. The SAM9G45 eMPU supports DDR2 and NAND flash memory interfaces for program and data storage. An internal 133MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and distributed memory including a 64kB SRAM which can be configured as a tightly coupled memory (TCM) sustains the high bandwidth required by the processor and the high speed peripherals. A true random number generator is embedded for key generation and exchange protocols.
  • 400MHz ARM926EJ-S ARM Thumb processor
  • 32kB Data cache, 32kB instruction cache, MMU
  • 133MHz Twelve 32-bit layer AHB bus matrix
  • Boot from NAND flash, SDCard, dataflash or serial dataflash
  • Reset controller (RSTC) with on-chip power-on reset
  • Selectable 32768Hz Low-power and 12MHz Crystal oscillators
  • Internal low-power 32kHz RC oscillator
  • One PLL for the system and one 480MHz PLL optimized for USB high speed
  • Two programmable external clock signals
  • Advanced interrupt controller (AIC)
  • Periodic interval timer (PIT), watchdog timer (WDT), real-time timer (RTT) & real-time clock (RTC)
  • Five 32-bit Parallel I/O controllers
  • 160 Programmable I/O lines multiplexed with up to two peripheral I/Os with Schmitt trigger input
  • DDR2 controller 4-bank DDR2/LPDDR, SDRAM/LPSDR
  • External bus interface
  • 64kB Internal SRAM, single-cycle access at system speed or processor speed through TCM interface
  • 64kB internal ROM, embedding bootstrap routine
  • LCD controller (LCDC) supporting STN and TFT displays up to 1280 x 860
  • ITU-R BT. 601/656 Image sensor interface (ISI)
  • Dual high speed USB host and a high speed USB device with on-chip transceivers


Automation & Process Control, Consumer Electronics

Product Information

SMART ARM based Microcontrollers
MSL 6 - Time on Label
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